CpE312 Course Syllabus

Course Syllabus: CpE312 - Hardware Definition Language

Instructor: Ronald Tantiado

Class Schedule: Every Wednesday, 10:00 am - 1:00 pm

Location: CpE Lab

Course Description: CpE312 is a laboratory-based course focused on Hardware Definition Languages (HDLs) used for designing and simulating digital circuits. Students will learn the fundamentals of HDL programming, explore various aspects of digital design, and develop hands-on experience in designing and simulating digital systems.

Course Outcomes: Upon successful completion of this course, students will be able to:

1. Understand the principles of digital logic design.
2. Write and analyze hardware description language (HDL) code.
3. Design, simulate, and test digital circuits using HDLs.
4. Apply HDL concepts to FPGA and ASIC design.
5. Collaborate effectively in a team to complete complex design projects.

Module Learning Outcomes:

Module 1: Introduction to HDLs

• Describe the importance of HDLs in digital design.
• Differentiate between VHDL and Verilog.
• Write basic VHDL and Verilog programs.

Module 2: Combinational Logic Design

• Design and simulate combinational logic circuits.
• Implement logic gates and multiplexers in HDL.
• Analyze and optimize combinatorial circuits.

Module 3: Sequential Logic Design

• Implement flip-flops, latches, and registers in HDL.
• Develop finite state machines (FSMs).
• Analyze and simulate sequential circuits.

Module 4: FPGA and ASIC Design

• Understand the differences between FPGAs and ASICs.
• Develop HDL code for FPGA and ASIC applications.
• Synthesize HDL code for FPGA and ASIC targets.

Module 5: Advanced Topics in HDLs

• Explore advanced HDL features, such as testbenches and parameterization.
• Implement memory elements and arithmetic circuits.
• Understand the concept of pipelining.

Module 6: Project Development

• Collaborate in teams to design and implement a digital system project.
• Apply HDL concepts to a real-world project.
• Present and demonstrate the project's functionality.

Assessment:

• Weekly Lab Assignments: 40%
• Midterm Project: 20%
• Final Project: 30%
• Class Participation and Quizzes: 10%

Grading Scale:

• A: 90-100%
• B: 80-89%
• C: 70-79%
• D: 60-69%
• F: Below 60%

Textbooks (published not older than 2018):

1. "Digital Design: A Systems Approach" by William J. Dally and R. Curtis Harting
2. "FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC" by Pong P. Chu
3. "VHDL for Digital Design" by Frank Vahid
4. "Verilog Digital System Design: With CDROM" by Zainalabedin Navabi
5. "FPGA-Based Implementation of Signal Processing Systems" by Roger Woods, John McAllister, and Gaye Lightbody